1. Field of the Invention
The present invention relates to the field of high density interconnected circuits, and more particularly, to high frequency high density interconnected circuits.
2. Background Information
Microwave systems are often composed of monolithic microwave integrated circuits (MMICs), other active microwave devices such as gallium arsenide (GaAs) transistors, passive microwave components and other non-microwave components such as logic and control structures.
A monolithic microwave integrated circuit or MMIC is an integrated circuit which is designed to operate at microwave frequencies. MMICs are normally fabricated in GaAs because of the much higher potential operating frequency which GaAs provides as compared to silicon. A typical MMIC may include one or more amplifiers, some passive components and one or more feedback loops which provide feedback from the output of an amplifier or circuit back to its input to establish a desired transfer function for that circuit.
It is known in the art to fabricate microwave systems from a variety of such components by providing a ceramic substrate having microstrip RF circuitry, DC supply lines (conductors), logic lines, control lines and contact pads fabricated thereon and by attaching devices and components such as MMICs, GaAs transistors, other microwave and supporting components to the substrate and connecting them to the circuitry on the substrate using wire bonds or tab interconnections.
Such fabrication techniques have a number of disadvantages which are discussed more fully in the related application Ser. No. 07/504,770, entitled "A High Density Interconnect Structure Including a Chamber".
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of digital and other electronic systems. For example, an electronic system such as a microcomputer which incorporates between 30 and 50 chips can be fully assembled and interconnected on a single substrate which is 2 inches long by 2 inches wide by 0.050 inch thick. The maximum operating frequency of such systems is normally, at present, less than about 50 MHz. Even more important than the compactness of this high density interconnect structure is the fact that it can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This reworkability or repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. 6000 from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to about 300.degree. C. which is above the softening point of the ULTEM.RTM. polyetherimide (which is in the vicinity of 235.degree. C.) and then cooled to thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E.I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pretreated to promote adhesion by reactive ion etching (RIE), the substrate and chips are then coated with ULTEM.RTM. 1000 polyetherimide resin or another thermoplastic and the Kapton film is laminated across the top of the chips, any other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are provided (preferably by laser drilling) in the Kapton.RTM. and ULTEM.RTM. layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton.RTM. layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the U.S. Patents and Patent Applications which are listed hereinafter.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 07/459,844, filed Jan. 2, 1990, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 07/457,023, filed Dec. 26, 1989, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; U.S. patent application Ser. No. 456,421, filed Dec. 26, 1989, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,546, filed Dec. 21, 1989, entitled "Hermetic High Density Interconnected Electronic System" by W. P. Kornrumpf, et al.; U.S. patent application Ser. No. 07/457,127, filed Dec. 26, 1989, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,545, filed Dec. 21, 1989, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al.; application Ser. No. 07/504,760, filed Apr. 5, 1990, entitled, "A Building Block Approach to Microwave Modules", by W. P. Kornrumpf et al.; application Ser. No. 07/504,821, filed Apr. 5, 1990, entitled, "HDI Microwave Circuit Assembly", by W. P. Kornrumpf, et al.; application Ser. No. 07/504,750 filed Apr. 5, 1990, entitled, "An Ultrasonic Array With a High Density of Electrical Connections", by L. S. Smith, et al.; application Ser. No. 07/504,803, filed Apr. 5, 1990, entitled, "Microwave Component Test Method and Apparatus", by W. P. Kornrumpf, et al.; application Ser. No. 07/504,753, filed Apr. 5, 1990, entitled, "A Compact High Density Interconnected Microwave System", by W. P. Kornrumpf; application Ser. No. 07/504,769, filed Apr. 5, 1990, entitled, "A Flexible High Density Interconnect Structure and Flexibly Interconnected System" by C. W. Eichelberger, et al.; application Ser. No. 07/504,751, filed Apr. 5, 1990, entitled, "Compact, Thermally Efficient Focal Plane Array and Testing and Repair Thereof", by W. P. Kornrumpf, et al.; application Ser. No. 07/504,749, filed Apr. 5, 1990, entitled, "High Density Interconnect Structure with Top Mounted Components", by R. J. Wojnarowski, et al.; application Ser. No. 07/504,770, filed Apr. 5, 1990, entitled, "A High Density Interconnect Structure Including a Chamber", by R. J. Wojnarowski, et al.; and application Ser. No. 07/504,748, filed Apr. 5, 1990, entitled, "Microwave Component Having Tailored Operating Characteristics and Method of Tailoring" by W. P. Kornrumpf, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
This high density interconnect system has been developed for use in interconnecting semiconductor chips to form digital systems. That is, for the connection of systems whose operating frequencies are typically less than about 50 MHz, which is low enough that transmission line, other wave impedance matching and dielectric loading effects have not needed to be considered.
The interconnection of microwave structures or devices intended to operate at GHz frequencies presents many problems, considerations and challenges not faced in the interconnection of digital systems which operate at frequencies of less than 50 MHz. Use of microwave frequencies requires consideration of wave characteristics, transmission line effects, material properties at microwave frequencies, the presence of exposed delicate structures on MMICs and other components and system and component characteristics which do not exist at the lower operating frequencies of such digital systems. These considerations include the question of whether the dielectric materials are suitable for use at microwave frequencies, since materials which are good dielectrics at lower frequencies can be quite lossy or even conductive at microwave frequencies. Further, even if the dielectric is not lossy at microwave frequencies, its dielectric constant itself may be high enough to unacceptably modify the operating characteristics of MMICs, GaAs transistors and other microwave components or structures which might be interconnected using a high density interconnect structure.
The above-listed application Ser. No. 07/504,821, entitled, "HDI Microwave Circuit Assembly" overcomes the problem of high dielectric constant of the high density interconnect structure dielectric material by removing the high density interconnect dielectric from portions of the chip which are overlay sensitive. By overlay sensitive, we mean that the operating characteristics of the device or component are different when the device or component is free of high density interconnect structure dielectric material than they are when the high density interconnect structure dielectric is disposed on the chip or structure or at least on overlay-sensitive portions of the chip or structure.
Unfortunately, the techniques disclosed in application Ser. No. 07/504,821 suffer from the disadvantage that the need to exclude the high density interconnect structure dielectric layer from the surface of overlay-sensitive microwave components severely restricts the surface area available for the routing of high density interconnect structure conductors since they cannot be routed over the area from which the dielectric layer is to be removed. Where chips are closely packed for maximum density, this essentially limits the high density interconnect structure to the routing of conductors in the streets and avenues portion of the structure which extends from the contact pads of one chip to the contact pads of the adjacent chip. For systems in which relatively low interconnection density is required, this limitation can be accommodated without serious impact on the system structure or operation. However, where a high density of interconnect conductors is required, such a restriction can make a system unroutable or require excessive numbers of layers of interconnect conductors or can require that the chips to be spaced further apart than would otherwise be necessary, just for the purpose of widening the streets and avenues to accommodate the required quantity of interconnect conductors.
Digital systems which are designed with very small features and/or which are designed to operate at frequencies in the GHz range can be sensitive to the presence of a dielectric layer thereover, even when they are not in the classic sense, microwave circuits in that they do not employ transmission lines and analog techniques. In such very high frequency digital systems, there is a need for a high density of interconnections which is similar to that need in such systems which operate in the 50 MHz and less frequency range. Removing the dielectric layer over the center of the chips severely restricts the available routing area.
Related application Ser. No. 07/504,770, entitled, "A High Density Interconnect Structure Including a Chamber" places overlay-sensitive chips in deep enough cavities that their upper surfaces are spaced below the upper substrate surface, laminates the initial high density interconnect dielectric layer to the chips and substrate in a manner which causes that dielectric layer to "sag" down onto the recessed surfaces of these chips. Metallization disposed on that first dielectric layer contacts each of the recessed contact pads and extends up the slope of the "sag" onto the planar portion of that initial dielectric layer. That initial dielectric layer is then removed from the overlay-sensitive portions of the chips. A second, taut dielectric layer is then laminated across the entire structure. This second dielectric layer is spaced from the overlay-sensitive portion of the recessed chips by the depth to which the tops of those chips are recessed. A normal high density interconnect structure metallization layer is then formed on this second dielectric layer with contact to the recessed contact pads being made via the portions of the initial metallization which are disposed over the top of the substrate.
While this accommodates the need, it is more cumbersome to fabricate than normal high density interconnect structures and is not directly applicable to flexible high density interconnect structures which are to be separated from their fabrication carrier (substrate) after fabrication as taught in related, incorporated by reference applications Ser. No. 250,010, entitled "High Density Interconnect With High Volumetric Efficiency" and Ser. No. 07/504,770, entitled, "A High Density Interconnect Structure Including a Chamber".
Accordingly, there is a need for a high density interconnect structure which accommodates the overlay sensitivity of many components without sacrificing the routing density of the high density interconnect structure, which is applicable to substrateless high density interconnect structures and whose fabrication is more similar to the standard fabrication process.